PARALLEL SESSION
C2L-G
Advanced CMOS Devices
THURSDAY - 11 September | 10:45 - 12:50
CHAIRS
Aarthi Jayakumar, Claire Fenouillet-Beranger
SESSION PROGRAM
10:45 - 11:10
Exploring 2D TMD pFET Gate Stack Scalability Towards 1nm Electrical Thickness
Tien Dat Ngo, Zaoyang Lin, Chelsey Dorow, Xiangyu Wu, Robert K. Grubbs, Daire Cott, Kaustuv Banerjee, I. Hoflijk, Thi...
11:10 - 11:35
Performance Improvement in Sub-2nm Node Nanosheet-FETs Through Optimization of Spacer Interface and Dopant Activation
Andrea Pondini, Pierre Eyben, Hiroaki Arimura, Philippe Matagne, Thomas Chiarella, Jishnu Ganguly, Clement Porret, Er...
11:35 - 12:00
First Demonstration of High Performance IGO TFT with Mobility >30cm2V-1s-1 and Ideal Stability at Cryogenic Temperatures Down to 2 Kelvin
Ke Hu, Mingliang Wang, Yue Zhao, Shuaidi Zhang, Wanming Wu, Jiawei Wang, Ling Li
12:00 - 12:25
Stacked 2D Monolayer MoS2 Nanosheet FET with Gate-all-Around and Top Gates Architecture
Fengben Xi, Himanshu Sharma, Xiangyu Wu, Daire Cott, Robert K. Grubbs, Pawan Kumar, Tom Schram, Jean-Francois de Marn...
12:25 - 12:50
Scaled Vertical Transport Gate-all-Around Nanostructured Channel (Nanosheet/Nanowire) Technology for Advanced CMOS Devices
Sylvain Pelloquin, Abhsishek Kumar, Sara Mannaa, Jonas Müller, Konstantinos Moustakas, Oskar Baumgartner, Ian O'Conno...