SEMICONDUCTOR INDUSTRY
KEYNOTE SPEAKERS
ANDREIA CATHELIN
Andreia Cathelin started electrical engineering studies at the Polytechnic Institute of Bucarest, Romania and graduated with MS from the Institut Supérieur d’Electronique du Nord (ISEN), Lille, France in 1994. In 1998 and 2013 respectively, she received PhD and “habilitation à diriger des recherches” (French highest academic degree) from the Université de Lille 1, France.
Since 1998, she has been with STMicroelectronics, Crolles, France, now Advanced R&D Design Technical Director and Technology R&D Fellow. Her focus areas are in the design of RF/mmW/THz and ultra-low-power circuits and systems. She is currently leading the RF Affinity team transversal inside the company, which enables knowledge creation and breakthrough solutions in the field towards open innovation and business impact.
Andreia is very active in the IEEE community since more than 15 years, strongly implied with SSCS and its Adcom (2 terms up to 2022). She is a member of the VLSI Symposium Executive Committee and has been the TPC chair of ESSCIRC 2020 and 2021 in Grenoble, and General Co-Chair of ESSCIRC-ESSDERC 2023 in Lisbon. She is as well IEEE RFIC Symposium TPC member and has been for 10 years involved with ISSCC as RF subcommittee chair and then member of the Executive Committee. She is as well an active founding member of the IEEE SSCS Women in Circuits group.
Andreia has authored or co-authored 150+ technical papers and 14 book chapters, has co-edited the Springer book “The Fourth Terminal, Benefits of Body-Biasing Techniques for FDSOI Circuits and Systems” and has filed more than 40 patents. She is currently Associate Editor for TCAS-I and OJ-SSCS IEEE journals.
Andreia has been a recipient and co-recipient of several awards with ISSCC and RFIC. She is as well the winner of the 2012 STMicroelectronics Technology Council Innovation Prize, and has been awarded an Honorary Doctorate from the University of Lund, Sweden, promotion of 2020.
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FD-SOI: Game changer in the IOT arena.
subtitle: Our circuits change the world!
Andreia Cathelin (Technical Director Advanced R&D Design and Technology R&D Fellow, STMicroelectronics, FR)
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This talk will bring the distinguished audience into the IoT land, presenting first the application fields, and then the integration challenges. We will then discuss about the FD-SOI CMOS technologies developed by STMicroelectronics in Europe, and how their particular features permit to tend towards the best-in-class energy efficiency and life time for such products, thanks to this technology opportunity. Sustainability aspects and implications will as well be discussed. We will demonstrate that technologists and IC designers can and should contribute to an overall carbon neutrality aspect over three axes: enable technologies that are energy-aware by construction, act for a system level global energy aware strategy and bring in circuit design solutions that always show 10x better energy reduction.
TSUNG-YUNG JONATHAN CHANG
Dr. Tsung-Yung Jonathan Chang is a TSMC Fellow and Senior Director leading memory IP development at TSMC. He is responsible for SRAM DTCO and memory IP development for advance technology nodes. Before joining TSMC, Dr. Chang was a principal engineer at Intel responsible for cache development for Enterprise server processors. He received B.S. degree from National Taiwan University, and M.S. and Ph.D. from Stanford University, all in electrical engineering. Dr. Chang is a fellow of IEEE, had served as the memory subcommittee chair from for ISSCC, TPC members of ISSCC, VLSI, associate and guest editors of Journal of Solid-State Circuits, and associate editor of IEEE Trans on VLSI. Dr. Chang has published more than 90 technical papers in IEEE conferences or journals and held twenty-five patents in embedded memory design.
Semiconductors at the Core of AI, HPC, and Edge Devices: Powering a New Era of Technological Innovation
Tsung-Yung Jonathan Chang (Senior Director TSMC, NL)
Christoph Heer (Head of Field Technical Support and Marketing TSMC EMEA, NL)
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Semiconductors have been instrumental in transforming human life, driving rapid advancements across numerous domains. The proliferation of personal computers, the internet, mobile devices, and high-performance computing (HPC) servers has introduced immense computing power and connectivity into everyday lives. As we progress into the era of Artificial Intelligence (AI), advanced semiconductor technologies are emerging as essential enablers, providing the computational power, memory capacity, and data transfer bandwidth required for AI applications. Innovations such as FinFET, nanosheet transistors, and 3D stacking are spearheading this technological evolution. Furthermore, specialized memory intellectual property (IP), including compute-in-memory architectures, is poised to significantly enhance power efficiency in AI systems. In the domain of specialty semiconductor technologies, embedded non-volatile memory (eNVM) plays an increasingly critical role in microcontroller (MCU) devices, enabling system-level optimization, programmability, low power consumption, and non-volatility. The demand for eNVM in advanced technology nodes, particularly 2xnm and beyond, is being driven by applications such as smart IoT devices, automotive MCUs, security MCUs, and smart power management. Emerging memory technologies like MRAM and RRAM are positioned as promising alternatives to eFlash for 2xnm and beyond. These memories are built on back-end storage elements, compatible with CMOS logic processes, and require fewer additional process steps. However, these advanced eNVM technologies face critical challenges, including small read windows, high write currents, limited write endurance, and data retention issues. To address these challenges, design-technology co-optimization (DTCO) strategies play a pivotal role in advancing MRAM and RRAM. These strategies include smart write algorithms with process-temperature-location compensation, optimized sensing circuits for improved read performance, high-retention OTP-like write schemes, and other innovations. Through the application of these DTCO methodologies, both MRAM and RRAM have demonstrated exceptional manufacturability, competitive performance, power, and area (PPA), as well as robust reliability.
CHRISTOPH HEER
Christoph Heer is heading the European Field Technical Support team of TSMC. His team is supporting the complete TSMC foundry offering from quarter micron down to actual leading edge technologies in N2 and A16 with design kit enablement and hands-on training.
Before joining TSMC mid of 2023 Christoph spent 12 years with Intel Mobile Communications and the Autonomous Solutions Division. He was the engineering manager of the Intel sites in Neubiberg/Munich.
Previous engagements were 11 years with Infineon Technologies and 4 years with Siemens Research. All senior management roles in the domain of advanced circuit design and IP provision.
Semiconductors at the Core of AI, HPC, and Edge Devices: Powering a New Era of Technological Innovation
Tsung-Yung Jonathan Chang (Senior Director TSMC, NL)
Christoph Heer (Head of Field Technical Support and Marketing TSMC EMEA, NL)
​date TBA
time TBA
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Semiconductors have been instrumental in transforming human life, driving rapid advancements across numerous domains. The proliferation of personal computers, the internet, mobile devices, and high-performance computing (HPC) servers has introduced immense computing power and connectivity into everyday lives. As we progress into the era of Artificial Intelligence (AI), advanced semiconductor technologies are emerging as essential enablers, providing the computational power, memory capacity, and data transfer bandwidth required for AI applications. Innovations such as FinFET, nanosheet transistors, and 3D stacking are spearheading this technological evolution. Furthermore, specialized memory intellectual property (IP), including compute-in-memory architectures, is poised to significantly enhance power efficiency in AI systems. In the domain of specialty semiconductor technologies, embedded non-volatile memory (eNVM) plays an increasingly critical role in microcontroller (MCU) devices, enabling system-level optimization, programmability, low power consumption, and non-volatility. The demand for eNVM in advanced technology nodes, particularly 2xnm and beyond, is being driven by applications such as smart IoT devices, automotive MCUs, security MCUs, and smart power management. Emerging memory technologies like MRAM and RRAM are positioned as promising alternatives to eFlash for 2xnm and beyond. These memories are built on back-end storage elements, compatible with CMOS logic processes, and require fewer additional process steps. However, these advanced eNVM technologies face critical challenges, including small read windows, high write currents, limited write endurance, and data retention issues. To address these challenges, design-technology co-optimization (DTCO) strategies play a pivotal role in advancing MRAM and RRAM. These strategies include smart write algorithms with process-temperature-location compensation, optimized sensing circuits for improved read performance, high-retention OTP-like write schemes, and other innovations. Through the application of these DTCO methodologies, both MRAM and RRAM have demonstrated exceptional manufacturability, competitive performance, power, and area (PPA), as well as robust reliability.