KEYNOTE SPEAKERS
KOFI MAKINWA
holds degrees from Obafemi Awolowo University, Ile-Ife (B.Sc., M.Sc.), Philips International Institute, Eindhoven (M.E.E.), and Delft University of Technology, Delft (Ph.D.). From 1989 to 1999, he was a research scientist at Philips Research Laboratories, where he designed analog front-ends for interactive displays and digital recording systems. In 1999, he joined Delft University of Technology, where he is currently a full Professor and Head of the Microelectronics Department. His research interests include the design of mixed-signal circuits, sensor interfaces, and smart sensors. This has resulted in 20+ books, 350+ technical articles and 40+ patents.
Dr. Makinwa is an IEEE fellow and a member of the Royal Netherlands Academy of Arts and Sciences. He is a co-recipient of 18 best paper awards, including two from the IEEE Journal of Solid-State Circuits (JSSC), two from the VLSI Symposium (VLSI) and five from the International Solid-State Circuits Conference (ISSCC). At the 70th anniversary of ISSCC, he was recognized as its all-time top contributing author. Dr. Makinwa has served on the program committees of several IEEE conferences, in particular as the Analog Subcommittee Chair of ISSCC. He has also been an AdCom member and Distinguished Lecturer of the IEEE Solid-State Circuits Society, a Guest Editor of the JSSC and an Editorial Board member of the Proceedings of the IEEE. He is currently a member of the VLSI ExCom, and a co-organizer of the Advances in Analog Circuit Design (AACD) Workshop and the IEEE Sensor Interfaces Meeting (SIM).
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CMOS Clocks: Just a Matter of Time!
Kofi Makinwa (TU Delft, NL)
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CMOS clocks are rapidly emerging as a compelling alternative to traditional MEMS and crystal-based clocks, offering fully integrated timing solutions with significant advantages in size, cost, and manufacturability. This talk will explore the technological evolution of CMOS-based timing, with a focus on LC and RC oscillator architectures. We will examine key design innovations—such as frequency-locked loops, calibration methods, and temperature compensation techniques—that have pushed CMOS clocks to performance levels suitable for a wide range of applications, particularly in the Internet of Things (IoT) and system-on-chip (SoC) domains.
YOUNGCHEOL CHAE
Youngcheol Chae is a full professor of electrical and electronic engineering at Yonsei University and the CEO of XO Semiconductor, Inc. Seoul, Korea. He received his B.S., M.S., and Ph.D. degrees from Yonsei University in 2003, 2005, and 2009, respectively. During his Ph. D. studies, he advanced oversampling ADCs through innovative design techniques including inverter-based amplifiers. From 2009 to 2011, as a post-doctoral researcher at Delft University of Technology in the Netherlands, he developed high-precision sensors and interface ICs. After joining Yonsei University in 2012, he leads a Yonsei Mixed-Signal IC group, focusing on innovative analog and mixed-signal circuits and systems for communication, sensing, and biomedical applications. This has resulted in 150+ peer-reviewed journal and conference papers and holds 50+ patents. Especially, his research team reported 65+ State-of-The-Art Chips in JSSC, ISSCC, and Symposium on VLSI Circuits.
Dr. Chae has been serving as a TPC member of the International Solid-State Circuits Conference (ISSCC), Asian Solid-State Circuits Conference (A-SSCC), and Custom Integrated Circuits Conference (CICC). He was a distinguished lecturer (DL) of IEEE Solid-State Circuits Society (SSCS). He received the ISSCC 2021 Takuo Sugano Award for Outstanding Far-East Paper, the Best Young Professor Award in Engineering from Yonsei University in 2018, the Haedong Young Engineer Award from the Institute of Electronics and Information Engineers (IEIE) Korea in 2017, the ISSCC Silkroad Award in 2017, the Outstanding Research Award of Yonsei University (2017, 2019, and 2020), and the Outstanding Teaching Awards of Yonsei University (2013, 2014). He is currently an Associate Editor of the Journal of Solid-State Circuits (JSSC) and Solid-State Circuits Letters (SSC-L).
Photon-counting SPAD X-ray sensor
​Youngcheol Chae (Yonsei University, KR)
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A SPAD X-ray detector is emerging as X-ray detectors for radiography and industrial applications, offering high speed, low dose, and high-resolution operations. This talk will introduce the world's first 7.2-inch wafer-level SPAD X-ray detector and its prospects. It addresses the key challenges facing high-performance X-ray detectors and demonstrates how the digital SPAD detector optimally addresses these challenges. We examine key design technologies for reducing noise and power consumption of 5 megapixels and maintaining the yield and image quality of wafer-scale detectors, which have made SPAD X-ray detectors suitable for a wide range of applications, particularly in medical X-ray.
NADINE COLLAERT
Nadine Collaert is imec fellow and director of imec’s advanced RF program. With a career spanning multiple decades, Nadine has contributed greatly to electronics research, and specifically innovated in the areas of semiconductor device design and technology. Throughout her career, she has worked on diverse projects, collaborated with various departments and groups, and made significant strides in advancing cutting-edge semiconductor technologies.
Expertise
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Advanced logic devices
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Electrical and electronics engineering
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Advanced RF
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Semiconductor device design
Career highlights
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(Co-)authored more than 400 papers published in international journals and conferences
Can GaN-on-Si Deliver the Wireless Future?
Nadine Collaert (imec, BE)
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Gallium Nitride on Silicon (GaN-on-Si) is rapidly emerging as a game-changing technology, poised to revolutionize wireless communication, particularly in the FR3 (7-20 GHz) spectrum. By combining GaN’s exceptional electron mobility and high breakdown voltage with the scalability and cost-efficiency of silicon substrates, GaN-on-Si is positioning itself as a formidable competitor to GaN-on-SiC, GaAs, and CMOS for 5G Advanced and 6G applications.
In infrastructure, GaN-on-Si is beginning to show promising performance in base stations operating at 28V and even 48V, offering high power density and efficiency while maintaining seamless compatibility with silicon manufacturing processes. For handset applications, GaN-on-Si shows immense promise, though challenges persist in achieving reliable enhancement-mode (E-mode) operation at lower voltages. Cutting-edge advancements in device architecture and material engineering are rapidly overcoming these hurdles, setting the stage for widespread adoption.
This keynote will delve into the latest breakthroughs in GaN-on-Si technology, including innovative thermal management strategies, reliability challenges and emerging solutions. It will also provide a comprehensive comparison of GaN-on-Si against competing technologies, highlighting its system-level advantages and sustainability benefits over traditional solutions. Attendees will gain valuable insights into how GaN-on-Si is enabling cost-effective, scalable, and high-performance solutions for next-generation wireless communication, while addressing the critical balance between performance, sustainability, and manufacturability in an ever-evolving RF landscape.
JOHANNA SEPULVEDA
Johanna Sepúlveda received her M.Sc. and Ph.D. degrees in Electrical Engineering – Microelectronics by the University of São Paulo, Brazil. She was a Senior Researcher in the area of security and emerging technologies at the University of South Brittany (France), INRIA (France) and at the Technical University of Munich (Germany). Currently she holds a position as the Airbus Senior Expert on Quantum-Secure Technologies and Technical Domain Manager for Quantum Technologies in all Airbus Defence and Space, being Chief Engineer of different European quantum initiatives such as the European Quantum Communication Infrastructure (EuroQCI). Also she is the vice-chair of the Strategic Advisory Board of Quantum Technologies for the European Commission and leader of the Strategic Industry Roadmap at the European Quantum Industry Consortium (QuIC). She has more than 15 years of experience in R&T and R&D in the area of security, networked systems, HPC and quantum technologies.​​​
Unlocking the Future: Quantum Technologies in the Era of Solid-State Electronics
Johanna Sepúlveda (Airbus Senior Expert on Quantum-Secure Technologies and Technical Domain Manager for Quantum Technologies in all Airbus Defence and Space, DE)
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Quantum technologies are rapidly transitioning from theoretical breakthroughs to practical applications that are set to transform industries. This keynote will explore how quantum technologies are driving innovations in quantum computing, secure communication, and high-precision sensing. We will discuss the integration of quantum systems with solid-state electronics, focusing on quantum processors, quantum cryptography, and sensors used in imaging, environmental monitoring, and navigation. By examining the advancements in material science, device fabrication, and system integration, this session will highlight the real-world impact of quantum technologies and their potential to reshape computing, security, and beyond.
PETER KUERZ
Peter Kuerz studied physics at Ludwig-Maximilians-University of Munich and earned his doctorate in experimental physics from the University of Constance. After completing two years of postdoctoral research at NTT Basic Research Laboratories in Japan, he joined ZEISS in 1996. Since 1999, he has focused on EUV lithography and currently serves as the Head of the High-NA EUV Field of Business, where he is responsible for the development and market launch of the next generation of ZEISS EUV optics. As a representative of the ZEISS EUV team and its partners, he received the Federal President's Award for Technology and Innovation in 2020 and the Werner-von-Siemens-Ring in 2024.​​​
From Test Tools to High-NA and Beyond: ZEISS's Role in Advancing EUV Lithography
Peter Kuerz (Carl Zeiss SMT GmbH, DE)
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Extreme Ultraviolet (EUV) lithography is a groundbreaking advancement in semiconductor manufacturing, enabling the production of increasingly powerful, cost effective, and energy-efficient microchips. Since achieving series production status in 2018 — over three decades after its initial demonstration in the mid-1980s — EUV lithography has established itself as a key technology in the semiconductor industry. ASML stands as the sole producer of EUV production systems, which are recognized as the most complex machines in the world.
This keynote will focus on the optical column, the core component of an EUV production system manufactured by ZEISS. We will explore the evolution of EUV optics technology, highlighting ZEISS's EUV journey since 1995. ZEISS has pioneered the creation of the world's most precise mirrors, overcoming unparalleled fabrication and metrology challenges. The assembly of EUV projection optics and illuminators has pushed the boundaries of mechatronics. Additional challenges have included optical design, coating technology, and optics lifetime strategies. We will outline the developments at ZEISS and its collaborative network over the past three decades, starting with test tools and progressing to 0.33 NA EUV, the current industry standard, as well as the recent introduction of High-NA EUV and conceptual work on Hyper-NA. These advancements are critical for sustaining Moore's Law well into the next decade.
Semiconductor Industry Session