PARALLEL SESSION
C2L-E
Innovations in pipelined ADCs
THURSDAY - 11 September | 10:45 - 12:50
CHAIRS
Burak Gonen, Mattias Palm
SESSION PROGRAM
10:45 - 11:10
A 12b 1GS/s SAR-Assisted Pipelined ADC with Gain-Error-Cancelled Dual-Path Amplifier and Partially Look-Ahead Parallel Quantization
Peng Wang, Yaning Wang, Lu Jie, Fule Li, Zhihua Wang
11:10 - 11:35
A 12-Bit 1-GS/s 5.1-mW Pipelined ADC Using an Open-Loop Floating Inverter Amplifier with Residue-Dependent Integration Time Compensation
Hongjiang Chen, Yuhang Peng, Liang Qi, Biao Wang, Sai-Weng Sin, Rui P. Martins, Mingqiang Guo
11:35 - 12:00
A Single-Channel 12-Bit 2GS/s 1.7GHz-Erbw Aperture-Error-Free Pipelined ADC with Flash-Embedded MDAC
Yaning Wang, Peng Wang, Guo Wei, Yihang Cheng, Hongsu Wang, Lu Jie, Nan Sun, Fule Li
12:00 - 12:25
A 200MS/s, 77dB-DR Two-Stage SAR ADC with Asynchronous Pipelining and Reference Snubbers
Jun Feng, Rares Bodnar, Filip Tavernier
12:25 - 12:50
A 68.5dB SNDR, 50MHz Bandwidth, 800MS/s Bandpass CT-Pipeline ADC in 65nm CMOS
Chaitanya Kumar, Shanthi Pavan