PARALLEL SESSION
A4L-C
Phased Locked Loops and FMCW Signal Generation
TUESDAY - 9 September | 13:50 - 15:55
CHAIRS
Nereo Markulic, Kevin Jun Yin
SESSION PROGRAM
13:50 - 14:15
A Type-I Reference Sampling PLL with Locking Region Tracking Achieving -261.8 dB FoMjitter, N and 7% Jitter Variation Over PVT
Weijia Zeng, Kaiyun Cao, Sirou Li, Rongjin Xu, Liangjian Lyu, Xing Wu, C.-J. Richard Shi
14:15 - 14:40
A 11.3-to-14.1 GHz Voltage-Domain Noise-Shaping Fractional-N Digital PLL
Yaqian Sun, Wei Deng, Haikun Jia, Angxiao Yan, Hongzhuo Liu, Junyang Yin, Baoyong Chi
14:40 - 15:05
A 152fsrms Ring-VCO-Based Injection-Locked PLL Using Multi-Phase Injection with Injection Timing and Pulsewidth Calibration
Zhen Li, Yuxiao Zhou, Haijin Zhang, Sen Jia, Xing Quan, Xiaodong Zhao, Yuanyuan Cui, Xunying Zhang
15:05 - 15:30
An 8.65-GHz 8th-Order-Polynomial DPD FMCW PLL Achieving 10-GHz/µs Chirp Slope with 0.039% rms Frequency Error and 3-GHz Chirp Bandwidth
Shuangfeng Kong, Zhiqiang Wu, Fenjun Chen, Zhiqiang Huang
15:30 - 15:55
A 7.7-to-9.8GHz SAR TDC FMCW ADPLL with −131dBFS Linearity for 111MHz/25.6us Chirp
Nenad Pavlović, Vladislav Dyachenko, Chuang Lu Lu, Lucien Breems