PARALLEL SESSION
B3L-G
Wireline Clock Generation and High Performance On-Chip Links
WEDNESDAY - 10 September | 10:25 - 12:05
CHAIRS
Harijot Singh Bindra, Declan Carey
SESSION PROGRAM
10:25 - 10:50
A 56-Gb/s PAM-4 Injection-Locked CDR
Johar Abdekhoda, Chongyun Zhang, Li Wang, Reza Sarvari, Reza Navid, C. Patrick Yue
10:50 - 11:15
A 12-to-20Gb/s, 2.93-pJ/Bit Jitter-Filtering Retimer with High Input Jitter Tolerance in 28nm CMOS
Inhyun Kim, Hyeonseok Lee, Ankur Kumar, Mingi Yeo, David Dolt, Taeyang Sim, Seongkwan Lee, Cheolmin Park, Minho Kang,...
11:15 - 11:40
A 0.65-pJ/B, 11-Gb/s/pin Transmitter Employing Edge-Controlled Crosstalk Cancellation for Near-Complete Suppression of Crosstalk-Induced Jitter
Yoochang Kim, Seunghoon Yi, Kwangho Lee, Haram Ju, Sung-Chul Lee, Young-Ha Hwang
11:40 - 12:05
A 23.5-fJ/b/dB 15.2-Gb/s/pin Switched-Capacitor-Driven On-Chip Link with Half-VDD DC Biasing and ISI Mitigation
Wonbin Lee, Soonwon Kwon, In-Woo Jang, Jae-Seung Jeong, Sara Kim, Kyeongha Kwon