PARALLEL SESSION
A3L-B
High-speed A/D and D/A converters
TUESDAY - 9 September | 10:55 - 12:35
CHAIRS
Claudio Nani, Francesco Conzatti
SESSION PROGRAM
10:55 - 11:20
A 2.5 GS/s 7.4 ENOB 6.8 mW VD-TD ADC with RC-Based Time-Residue Processing
Dong Suk Kang, Ken Li, Tzu Han Wang, Shaolan Li
11:20 - 11:45
20 GS/s 46 dB SNDR 16x Time-Interleaved Pipelined-SAR ADC Using Bulk Calibration for Comparator Offset and Bandwidth Mismatch
Patrick Artz, Qihang He, Sebastian Linnhoff, Frowin Buballa, Marcel Runge, Enne Wittenhagen, Philipp Scholz, Friedel...
11:45 - 12:10
A 7b 30GS/s 0.032mm² CI-SAR TIADC in 28-nm CMOS with Fractional-Delay FIR Filter Based Full-Digital Background Timing Skew Calibration
Jongho Kim, Gyuchan Cho, Hwankyu Song, Hyeonsik Kim, Jintae Kim
12:10 - 12:35
A 28nm 8-Bit 32-GS/s DAC Achieving > 55dBc/> 40dBc SFDR Up to 5.2GHz/13.6GHz Using 4-Channel NRZ Time-Interleaving with Background Calibration for Direct Digital Signal Synthesis
Sihao Chen, Chengyu Huang, Huazhong Yang, Xueqing Li