PARALLEL SESSION
B3L-C
Digital Circuits and Techniques
WEDNESDAY - 10 September | 10:25 - 12:05
CHAIRS
Martin Brox, Marisa Lopez-Vallejo
SESSION PROGRAM
10:25 - 10:50
Total Energy Minimization of Duty-Cycled, Multi-Vdd SoCs with Execution-Time Guarantees
Chi-Hsiang Huang, Kevin Patiño Sosa, Arindam Mandal, Julian Arenas, Diego Peña-Colaiocco, Visvesh Sathe
10:50 - 11:15
A Highly Reliable and Anti-Cloning STT-MRAM Reconfigurable Physical Unclonable Function
Hongrui Meng, Yajun Wu, Shengchao Zhou, Teng Zou, Tai Min, Shaohao Wang, Yufeng Xie
11:15 - 11:40
A 512 kb 0.069 µm² Logic 3T GCRAM with 27 µs Retention Time at 85°C in 16 nm FinFET
Andac Yigit, Ahmet Avcioglu, Robert Giterman, Leo Johansson, Inon Lavi, Eli Leizerovitz, Xinwei Li, Christoph Mueller...
11:40 - 12:05
A Coupled Oscillator Based Ising Chip with a Fully-Connected Annealing Core, a Hamiltonian Engine, and a RISC-V Gradient Search for Solving 2,500+ Spin Combinatorial Optimization Problems
Chaohui Li, Yonghwan Hong, Alex Vanasse, Tahmida Islam, Peter Kreye, Xunqi Li, Ruihong Yin, Hao Lo, William Moy, Chri...