WORKSHOPS
W7 (Dissemination workshop): Tips and Tricks for a Successful Multi-Project-Wafer (MPW) Chip
14:00 - 17:30 ROOM R6
CHAIR
Thomas Drischel (Fraunhofer IIS, BE)
ABSTRACT
In Multi-Project-Wafer (MPW) prototyping, multiple design iterations extend the initial timeline and increase costs. In this workshop, Europractice experts will discuss the best practices and lessons learned from the MPW prototyping process, sharing practical tips and tricks on avoiding common errors, optimising the design for tape-out, and troubleshooting the issues that may arise.
We will also discuss how to select the appropriate test and packaging options, especially for smaller advanced nodes. We will also explain how to access the Europractice platform, which provides affordable MPW fabrication services in a wide range of technologies, including ASICs, MEMS, Photonics, Microfluidics, Flexible Electronics, and more.
PROGRAM
14:00 - 14:15
Introduction to MPW Fabrication
Romano Hoofman (imec / Europractice, BE)
For 30 years, Europractice have supported European universities, research institutes, and their spinouts with affordable and easily accessible design tools, fabrication services, and training courses. This talk will provide an overview of Multi-Project Wafer (MPW) services, highlighting cost-sharing benefits and access to advanced technologies. It will cover Europractice's diverse technology portfolio with 22 foundries, extensive technical support, and share success stories to demonstrate practical applications.
​
14:15 - 15:00
RTL Signoff Analysis
Kwan Cheung (UKRI-STFC / Europractice, UK) and Domas Druzas (UKRI-STFC / Europractice, UK)​
Functional bugs remain to be one of the top reasons for costly respins. In this talk, we discuss how we can catch critical design issues early - at the Register Transfer Level (RTL). By using the right tools for the task, we will not only minimise the chance of a functional bug ending up on the silicon, but also shorten the overall design cycle by reducing the time spent on debugging. The types of checks that will be covered in this talk include clock domain crossing checks, x-prop checks and design-for-testability checks.
​
15:00 - 15:30
Choosing a Technology for Your Design - Part I
Domas Druzas (UKRI-STFC / Europractice, UK)
With so many technology nodes and options available, it can be a daunting task to choose one that is best suited for a project. In this section, we explore fabrication technologies offered via Europractice and different considerations designers need to consider in order to successfully implement their ideas.​
​
15:30 - 16:00
Coffee break
​​​
16:00 - 16:15
Choosing a Technology for Your Design - Part II
Domas Druzas (UKRI-STFC / Europractice, UK)
​
16:15 - 17:00
Design Finishing and Sign Off
Tobias Vanderhenst (imec / Europractice, BE) and Syed Shahnawaz (Fraunhofer IIS / Europractice, DE)
In "Design Finishing and Sign-off," we focus on the preparation and completion of the tape-out process to guarantee a seamless execution. This involves final verification, procurement, export, MPW preparation, and GDS delivery.​
​
17:00 - 17:30
Selecting a Packaging Solution
Thomas Drischel (Fraunhofer IIS / Europractice, BE)
To select the right package for your ASIC, start with an overview of available packaging options. Then, create a bonding diagram to ensure optimal connectivity and performance. Finally, follow best practices to enhance reliability in your ASIC packaging process.
BIOSKETCHES
Thomas Drischel (Chair)
Thomas Drischel holds a degree in microelectronics from the University of Applied Sciences in Nuremberg. He joined Fraunhofer in 1998 and has been involved in prototyping and small volume manufacturing projects. He leads the Virtual ASIC Foundry group at Fraunhofer IIS, which offers design and fabrication services for custom integrated circuits. Within Europractice, Thomas Drischel oversees fabrication in a variety of technologies from different semiconductor manufacturers, such as ams OSRAM, IHP, GlobalFoundries, X-FAB, Fraunhofer IISB, and UMS.
​
Kwan Cheung
Kwan Cheung is currently the verification lead at the National Microelectronics Support Centre at UKRI STFC. She has over 18 years of experience in supporting and training Europractice users in using industry-standard digital IC design and verification tools from major EDA vendors including Synopsys, Cadence and Siemens.
​
Domas Druzas
Domas Druzas is currently leading a digital IC design and implementation group at UKRI supporting Europracice activities. His primary role is developing EDA design methodologies for Europractice training and technical support activities.
​
Romano Hoofman
Romano Hoofman is Strategic Development Director at imec.IC-link since 2016. He is currently responsible for the innovation programs of the unit and for the coordination of the EUROPRACTICE Service. He started his career in industry, where he worked as a Principal Scientist at Philips Research and later on NXP Semiconductors. He covered many different R&D topics, ranging from CMOS integration, advanced packaging, thin film batteries, photovoltaics and (bio)sensors. Romano received his PhD from the Technical University of Delft in 2000, where he investigated charge transport in semi-conducting polymers. He has authored more than 30 publications and holds more than 10 patents in various research areas.
​
Tobias Vanderhenst
Tobias Vanderhenst is currently leading industrial and academic tapeout operations at imec.IC-link and Europractice. He started his career at imec in 2008. Today, he leads a team responsible for the support of multiple tapeouts in different technologies, including TSMC, X-FAB, UMC, and Science.