WORKSHOPS

9:30 - 10:15

State of Art eNVM Solutions

Glavine Yeh (TSMC, TW)

The evolution of embedded non-volatile memory technologies continues to be a cornerstone of innovation in the semiconductor industry, driving advancements across diverse applications. In this speech, we will explore the latest developments in state-of-the-art embedded memory solutions, offering a comprehensive overview of their distinctive features, benefits, and challenges. Starting with the foundational technology of traditional embedded flash memory, we will transition into cutting-edge emerging solutions such as Resistive RAM (ReRAM), Ferroelectric transistor, Phase Change Memory (PCM), and Magnetic RAM (MRAM). By examining their underlying mechanisms, performance characteristics, and potential applications, this discussion will illuminate how these technologies are redefining the possibilities for next-generation systems in automotive, industrial, IoT, and beyond.

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10:15 - 11:00

RRAM Design Challenge and Solution

Yu-Der Chih (TSMC, TW)

Resistive RAM (RRAM) is emerging as a promising alternative to conventional charge-based flash technology for a wide range of embedded applications. As a backend-of-line memory, RRAM offers minimal interaction with CMOS frontend devices and is fully compatible with CMOS logic circuits. Requiring only 2 to 3 additional process steps, byte-alternative, fast write speeds, and provides high write endurance. Despite these advantages, RRAM faces several unique challenges, including read window drift, high write current, and data retention issues during the packaging process.

In this talk, I will present solutions through design-technology co-optimization (DTCO) to address these challenges. Specifically, I will discuss the implementation of advanced sensing schemes for read operations, adaptive write bias techniques for write processes, smart write algorithms for enhanced reliability, design for testability (DFT) methods for effective screening, and the RRAM-OTP to improve data retention during the packaging process. These optimizations aim to enhance the performance and reliability of RRAM, establishing it as a viable replacement for traditional flash memory in embedded systems.

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11:00 - 11:30

Coffee break

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11:30 - 12:15

AI Acceleration with Ferroelectric Transistors

Hussam Amrouch (Technical University of Munich, DE)

​In this talk, we will showcase the latest advancements in Ferroelectric transistors (FeFETs), spanning from traditional In-Memory Computing (IMC)-based hardware accelerators to monolithic 3D integration using advanced back-end-of-line (BEOL) thin-film transistors. We will elucidate the inherent challenges posed by ferroelectric stochasticity along with temperature effects. Finally, we will demonstrate the synergy between IMC and brain-inspired hyperdimensional computing and how technology/algorithm co-optimization is the key to realize reliable in-memory computing using FeFET devices.

 

12:15 - 13:00

MRAM Design Challenge and Solution

Eric Wang (TSMC, TW)

With the tremendous advances in the past two decades, Spin-Transfer Torque Magnetic Random-Access Memory (STT-MRAM) has been widely adopted by advanced foundries and IDMs for its superior data retention, endurance, and fast read/write speed, making it ideal for high-performance automotive-grade MCUs and next-gen software-defined vehicles.  This talk reviews the past and recent advancements in STT-MRAM technology and circuit designs for automotive applications.  Architecture of STT-MRAM cells and features of memory array will be reviewed.  Design-Technology Co-Optimization (DTCO) techniques to enhance operation windows, reliability, and manufacturing yield of MRAM in advanced CMOS will be discussed.

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13:00 - 14:00

Lunch​

Glavine Yeh (Chair)

Glavine Yeh is Sr. Program Manager, in charge of FinFET university program at TSMC Europe. Prior to this role, Glavine was Technical Manager, focusing on embedded non-Volatile Memory (eNVM) technologies and successfully driving eNVM technologies as the most important growing business at TSMC Europe. Glavine joined TSMC in 1997, he served as manager of customer service for the Japan region. In 2008, he joined TSMC Europe, responsible for engaging on technologies and enabling new product development. He received his M.S. in Material Science and Engineering from National Tsing Hua University in Taiwan.

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Hussam Amrouch

Hussam Amrouch is Professor heading the Chair of AI Processor Design within the Technical University of Munich (TUM). He is, additionally, the head of Brain-inspired Computing at the Munich Institute of Robotics. Further, he is the head of the Semiconductor Test and Reliability at the University of Stuttgart, Germany. He is also the Academic Director of TUM Venture Labs for Semiconductor. He received his Ph.D. degree with the highest distinction (summa cum laude) from KIT in 2015. He has 300 publications (including over 125 articles in many top journals such as Nature Communications) in multidisciplinary research areas covering semiconductor device physics, circuit design and computer architecture. His research interest is AI acceleration, emerging technologies, in-memory computing with a special focus on reliability, and cryogenic circuits for quantum computing. His research in AI chips and reliability have been funded by the German Research Foundation (DFG), Bavarian ministry of economy, Bavarian ministry of science, Advantest Corporation, and the U.S. Office of Naval Research.

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Yu-Der Chih

Yu-Der Chih received the B.S. degree in physics from National Taiwan University, Taipei, Taiwan, in 1988, and the M.S. degree in electronics engineering from National Tsing Hua University, Hsinchu, Taiwan, in 1992.,From 1992 to 1997, he was a Design Engineer of Ethernet transceiver circuits for data communication with Macronix, Hsinchu, and a Circuit Design Engineer of SDRAM with Powerchip, Hsinchu. In 1997, he joined Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, where he was involved in the development of embedded nonvolatile memory IP, including embedded flash, OTP, MTP, and emerging memory. He is currently a TSMC Academician and the Director of the Embedded Nonvolatile Memory Library Department, Memory Solution Division.

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Yih Wang

Yih Wang received his Ph.D. degree in electrical and computer engineering from University of Florida, Gainesville, under the tutelage of Dr. Chih-Tang Sah.  His industry career began with Intel’s logic technology development group in 2001, where he was a Sr. Principal Engineer, leading the development of critical technologies for embedded memories from 90nm to 14nm CMOS technologies.  He received three Intel Achievement Awards for his contributions on development of embedded SRAM and DRAM technologies.  He is currently a director in the design and technology platform group at TSMC.  He is the author and co-author of more than 70 peer-reviewed journal and conference papers and 180 U.S. patents.   He served on the technical program committee of VLSI Symposium from 2016 to 2018 and is a technical program committee member of ISSCC (2021-present).​​