WORKSHOPS
W2 OpenPDK Initiative: Technology - Devices - ICs
09:30 - 13:00 ROOM R3
CHAIR
Wladek Grabinski (IHP OpenPKD, CH)
ABSTRACT
The development of open-source Process Design Kits (PDKs) is crucial for democratizing access to advanced semiconductor technologies. IHP’s OpenPDK initiative bridges the gap between academia, startups, and the semiconductor industry by offering a fully open and manufacturable SG13G2 BiCMOS technology platform for analog/RF, mixed-signal, and digital IC applications. Aligning with the EU Chips Act, this initiative emphasizes open collaboration to overcome economic and technical barriers in semiconductor innovation. The workshop introduces SG13G2 OpenPDK and Free and Open-Source Software (FOSS) tools for IC designs, including Verilog-A devices, schematic capture, SPICE simulation, layout, physical verification in advanced design flow up to final typeout.
PROGRAM
Program to be structured according to the following schedule:
​09:30 - 11:00
Session 1
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​11:00 - 11:30
Coffee break​
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11:30 - 13:00
Session 2​
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Talks - please complete with speaker names and countries)
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IHP OpenPDK Roadmap
Speaker's name (IHP OpenPDK, Country)
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Verilog-A Device Model Standardization
Speaker's name (OpenVAF and University of Ljubljana, SI)
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Advances in RF/EM Component Modeling
Speaker's name (OpenEMS/ELMER and University of Duisburg-Essen, DE)
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Analog/RF IC Design Tools
Speaker's name (QUCS-S and London MET, UK)
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Analog IC Flow Automatization
Speaker's name (MOSAIC and Infineon, Country)​
BIOSKETCHES
Wladek Grabinski
Wladek Grabinski received the Ph.D. degree from the Institute of Electron Technology, Warsaw, Poland, in 1991. From 1991 to 1998 he was a Research Assistant at the Integrated Systems Lab, ETH Zürich, Switzerland, supporting the CMOS and BiCMOS technology developments by electrical characterization of the processes and devices. From 1999 to 2000, he was with LEG, EPF Lausanne, and was engaged in the compact MOSFET model developments supporting numerical device simulation and parameter extraction. Later, he was a technical staff engineer at Motorola, and subsequently at Freescale Semiconductor, Geneva Modeling Center, Switzerland. He is now a consultant responsible for modeling, characterization and parameter extraction of MOS transistors for the design of RF CMOS circuits. His current research interests are in high-frequency characterization, compact modeling and its Verilog-A standardization as well as device numerical simulations of MOSFETs for analog/RF low power IC applications. He is currently consulting on the development of next-generation compact models for the VLSI integration and OpenPDK IC simulation. He is an author of the reference “Compact/SPICE Modeling” chapter in the Springer Handbook of Semiconductor Devices, and also authored or coauthored more than 70 papers. Wladek has established ESSDERC TPC Track3: "Device and Circuit Compact Modeling" as well as was serving as a member of the IEEE EDS Compact Modeling Technical Committee, European representative in the ITRS Modeling and Simulation Working Group; organization committees of ESSERC, TPC of SBMicro, SISPAD, MIXDES Conferences; reviewer of the IEEE TED, IEEE MWCL, IJNM, MEE, MEJ. He was a Member At Large of Swiss IEEE ExCom and mentor of the EPFL IEEE Student Branch. Wladek is involved in activities of the MOS-AK Association and serves as a coordinating R&D manager since 1999.
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To be completed
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