WORKSHOPS
CHAIR
Wladek Grabinski (IHP OpenPKD, CH)
ABSTRACT
The development of open-source Process Design Kits (PDKs) is crucial for democratizing access to advanced semiconductor technologies. IHP’s OpenPDK initiative bridges the gap between academia, startups, and the semiconductor industry by offering a fully open and manufacturable SG13G2 BiCMOS technology platform for analog/RF, mixed-signal, and digital IC applications. Aligning with the EU Chips Act, this initiative emphasizes open collaboration to overcome economic and technical barriers in semiconductor innovation. The workshop introduces SG13G2 OpenPDK and Free and Open-Source Software (FOSS) tools for IC designs, including Verilog-A devices, schematic capture, SPICE simulation, layout, physical verification in advanced design flow up to final typeout.
PROGRAM
​09:30 - 10:00
IHP OpenPDK Roadmap
Melik Yazici (IHP, DE)
​Now in its third year, the IHP OpenPDK initiative has made remarkable progress in providing open-source access to IHP's advanced BiCMOS technology. This presentation will highlight the initiative's key achievements over the past year, including improvements to PDK components, greater compatibility with open-source EDA toolchains and increased community engagement. The current roadmap will be outlined, challenges will be addressed, and the outlook on the upcoming transition from the alpha phase to the first official OpenPDK release by the end of 2025 will be provided. Whether you are a developer or contributor to the project, or are simply curious about it, you will gain a comprehensive overview of its current state and future goals. Additionally, we will present an overview and first results of IHP's free, open-source MPW (Multi-Project Wafer) programme for 2024 and 2025. There will be a special focus on the September 2025 shuttle, which is an important milestone for collaborative modeling developments using open-source flows. The session will conclude with a discussion about the evolving framework and criteria for open-source MPW opportunities from IHP from 2026.​
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10:00 - 10:30
The OpenVAF Verilog-A Compiler for the OpenPDK Ecosystem
Árpád Bűrmen (University of Ljubljana, SI)
OpenVAF is a free and open source Verilog-A compiler for compact models. It is fast (most models compile in under a second) and produces fast models (faster than ADMS). Among other, its ecosystem includes the Ngspice circuit simulator, the VACASK circuit simulator, and the Verilog-A Distiller model converter. The importance of automated model conversion from legacy SPICE3 C format into Verilog-A is highlighted. An overview of recent progress is given, benchmarks simulations with OpenVAF-generated models are presented, and a roadmap for future development is laid out.
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10:30 - 11:00
User-friendly FDTD EM Workflow for IHP OpenPDK with Automatic Meshing
Volker Muehlhaus (Consulting & Software GmbH, DE)
A new user-friendly workflow for EM analysis of RFIC layouts is presented, which significantly simplifies model creation. The new workflow is based on openEMS, with an additional software layer that specifically targets RFIC EM use cases. One major difficulty in openEMS has always been the manual setup of an appropriate simulation mesh - this problem is solved by the new workflow which provides automatic geometry-driven mesh setup. Model geometries are read directly from GDSII, with no need for prior conversion. Overall, the additional software layer in this new workflow leads to model setup that is much easier to navigate than standard openEMS code, easier to re-use and makes this workflow suitable even for users with little EM experience.​​
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​11:00 - 11:30
Coffee break​
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11:30 - 12:15​​​
Building Component Libraries for Use with the IHP OpenPDK and FOSS Tools
Mike Brinson (London Metropolitan University, UK)
The release by IHP-GmbH in 2023 of a Process Design Kit (PDK) for an open-access 130nm BiCMOS node allows free access to a PDK for analogue, mixed signal and RF IC Design. An important goal of the IHP-GmbH initiative is to provide semiconductor process and IC layout data for creating manufacturable IC designs, using FOSS software. This presentation reports on the current state of the development of component libraries for IC design using the IHP SG13G2 process node, including background and the capabilities currently implemented, or under development, with the FOSS software packages Qucs-S, Ngspice and OpenVAF. The current releases of these further expand on previous generations of FOSS tools to include more advances in schematic capture, PDK integration, improved circuit analysis/simulation, and high resolution output data visualisation. Throughout the presentation a series of simulation examples and case studies are discussed. These have been chosen specifically to illustrate the capabilities and application of the FOSS tools in analogue, mixed mode analogue/digital and RF design. All the FOSS software introduced in this talk are freely available and can be downloaded using the internet links provided.​​
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12:15 - 13:00
Analog IC Flow Automatization
Mirjana Videnović-Mišić (Infineon, AT)​​
Despite the rise of digitalization and artificial intelligence, European manufacturers continue to differentiate themselves through products with unique analogue features. However, the traditional analogue design workflow, largely unchanged over the past 30 years, remains a bottleneck to time-to- market. Characterized by manual interaction and a lack of standardization, this approach hinders innovation and efficiency. This talk will explore the challenges and future directions of Analog IC Design Flow Automation, focusing on raising the abstraction level of analog IC design to improve productivity and reduce design time, leveraging the MOSAIC (Modular Open Source Analog IC) Orchestrator as a solution for integration of diverse tools and methodologies and the need for more standardized and inclusive analog IC design methodologies to facilitate collaboration and knowledge sharing. By addressing these challenges, we can unlock the full potential of Analog IC Design Flow Automation, enabling European manufacturers to maintain their competitive edge in a rapidly evolving technological landscape.​
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13:00 - 14:00
Lunch
BIOSKETCHES
Wladek Grabinski (Chair)
Wladek Grabinski received his PhD at ITE Warsaw in 1991 and has worked at ETH Zürich, EPFL, Motorola/FSL on CMOS/BiCMOS modeling and characterization. He now consults on compact modeling, Verilog-A standardization, and OpenPDK development for RF/analog ICs. He authored the reference “Compact/SPICE Modeling” chapter in the Springer Semiconductor Handbook and published over 70 papers. Wladek is active in MOS-AK, ESSERC, and IEEE committees, promoting open-source SPICE modeling and FOSS design for next-generation IC applications.
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Mike Brinson
Mike Brinson received a first class honours BSc degree in the Physics and Technology of Electronics from the United Kingdom Council for National Academic Awards in 1965, and a PhD in Solid State Physics from London University in 1968. Since 1968 Dr. Brinson has held academic posts in Electronics and Computer Science. From 1997 till 2000 he was a visiting Professor of Analogue Microelectronics at Hochschule, Breman, Germany. Currently, he is a Professor at the Centre for Communication Technology Research, London Metropolitan University, UK. He is a Chartered Engineer (CEng) and a Fellow of the Institution of Engineering and Technology (FIET), a Chartered Physicist (CPhys), and a member of the Institute of Physics (MInstP). Prof. Brinson joined the Qucs project development team in 2006.
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Árpád Bűrmen
Árpád Bűrmen received his PhD in electrical engineering from University of Ljubljana in 2003 where he is a tenured professor of electrical engineering. His research interests include analog circuits, circuit simulation, design automation, and optimization algorithms. He co-authored the SPICE OPUS and the VACASK circuit simulators, the Verilog-A Distiller model converter, and the PyOpus design automation library. He published over 40 papers in international journals and co-authored a book titled "Circuit simulation with SPICE OPUS : theory and practice" published by Birkhäuser (Springer) in 2009.
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Volker Muehlhaus
Volker Muehlhaus received the Dr.-Ing. degree in electrical engineering from Ruhr-University Bochum, Bochum, Germany, in 1994. From 1989 to 1994, he was a Research Assistant with the Microwave Measurement Group at the Institute of High Frequency Engineering, Ruhr-University Bochum. In 1993, he started his engineering company and initially worked on custom RF circuit design for industrial applications. Over time, the company focus shifted to workflow development for RF layout and simulation. From 1998 to 2012, Volkers company was responsible for European sales and support of RF EM simulation software from Sonnet Software (planar 3D MoM) and IMST (3D FDTD), where Volker introduced various customized EM workflow integrations and cluster solutions for massively parallel EM simulation. Since 2012, Volker is working as an independent EM specialist, with a focus on RFIC EM simulation solutions.
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Mirjana Videnović-Mišić
Mirjana Videnović-Mišić received Dipl.Ing, M.Sc. and PhD degree in Electronics and Microelectronics engineering from the University of Novi Sad, Serbia, in 1997, 2003 and 2009 respectively. In 2008 she founded the Team for analog and radio frequency integrated circuit design (ICreate) at the University of Novi Sad, Serbia. In 2010 she joined Faculty of Technical Sciences, University of Novi Sad as an assistant professor covering the topics from semiconductor devices modeling to analog and radio-frequency integrated circuit design. In 2014/2015 she was Fulbright Visiting Scholar and from 2015-2018 she was the Marie Currie Individual Global Fellowship recipient. Both fellowships were executed in cooperation with the Berkeley Wireless Research Center, University California at Berkeley. From 2018-2022 she was with Silicon Austria Labs and since October 2022 she is part of AnaGen team at Infineon. Dr. Videnović-Mišić is passionate about emerging technologies and their usage in analog/MS IC design automation. She is big proponent of the open-source and former member of IEEE SSCS Technical Committee for Open-Source Ecosystem.
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Melik Yazıcı ​
​Melik Yazıcı is an electronics engineer specializing in CMOS analog, digital, and mixed-mode integrated circuits, infrared detectors and readouts, and passive semiconductor device modeling. He earned his B.Sc. and Ph.D. degrees in Electronics Engineering from Sabancı University, Istanbul, Turkey, in 2008 and 2016, respectively. Since 2022, he has been with IHP Microelectronics, where he contributes to modeling poly resistors and advancing semiconductor technology development. Combining deep academic expertise with industry experience, Melik brings a strong background in circuit design, device modeling, and applied research to his work, bridging theoretical understanding with practical innovation.