WORKSHOPS

 

Session 1: Analog In-Memory Computing Accelerators

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9:30 - 10:00

Heterogeneous Analog In-Memory Computing Accelerators for AI

Irem Boybat (IBM Research Europe, CH)

AI workloads are inherently data-intensive and demand massive parallel computation, placing significant strain on conventional computing architectures. Traditional von Neumann systems struggle to meet these demands due to the increasing overhead of data movement between memory and processing units. Analog In-Memory Computing (AIMC) offers a promising alternative by performing computations directly within memory arrays, significantly improving energy efficiency. This workshop will explore heterogeneous AIMC architectures that combine different types of accelerator nodes to enable efficient deployment of deep learning inference at the edge. A specialized embedded neural processing unit will be presented, supporting diverse operation types and precision levels through this architectural mix. The design incorporates AIMC tiles based on Phase-Change Memory (PCM) to perform energy-efficient matrix-vector multiplications while providing high non-volatile on-chip weight capacity. The workshop will also examine how such heterogeneous architectures can be adapted to specific application domains, with focused case studies from physics and bioinformatics.​​

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10:00 - 10:30

Area and Energy-Efficient Data Converters for Analog In-Memory Computing

Taekwang Jang (ETH Zurich, CH)

As the demand for energy-efficient and high-performance computing continues to grow, analog in-memory computing (AIMC) has emerged as a promising solution to overcome the limitations of digital computing. By performing computations directly within memory arrays, AIMC significantly reduces data movement and overall energy consumption. However, the area and power overhead of data converters accessing the memory crossbar array remains a critical concern, especially in large-scale deployments. This talk presents recent advancements in the design of area- and energy-efficient data converters for AIMC systems. Various ADC architectures, such as successive approximation, charge injection, and flash ADCs, along with related circuit techniques, will be discussed. ​

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10:30 - 11:00 

Accuracy Simulation of Analog In-Memory Computing Accelerators

Bipin Rajendran (King's College London, UK)

Analog In-Memory Computing (AIMC) has emerged as a promising solution to address the growing computational demands of deep neural networks (DNNs), offering significant reductions in latency and energy consumption. However, nanoscale memory devices used in AIMC hardware exhibit non-idealities such as programming noise, read noise, and conductance drift, which can degrade model accuracy if software-trained networks are directly deployed on hardware. In this talk, we will discuss strategies for hardware-aware training that help mitigate these effects, enabling AIMC accelerators to achieve accuracy levels comparable to software baselines. Additionally, we introduce the IBM Analog Hardware Acceleration Kit (AIHWKit), an open-source Python library that facilitates the simulation of DNN training and inference on AIMC hardware, providing a valuable tool for researchers to evaluate model accuracy, hardware non-idealities, and deployment strategies for AI applications.​

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11:00 - 11:30

Coffee break 

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Session 2: Near-Memory Computing for Data-Intensive Applications

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11:30 - 12:00

A Tale of Two: Architecture and System Approaches for Exploring Compute Memories

Giovanni Ansaloni (EPFL, CH)

The demise of scaling laws and the unabated increase in AI workloads is fostering disruptive approaches for next-generation computing architectures. Among those, compute memories (CMs) are especially attractive: they have the potential to reduce every-more costly data movements, while leveraging the massive parallelism offered by the hierarchical organization of memory arrays.

Nonetheless, the development of CM solutions is hampered by the paucity of exploration frameworks. In this talk, I illustrate two approaches which aim to address this challenge, based on open hardware and system simulation frameworks, respectively. The talk details the architecture of two CMs (both resulting in >100X performance increase compared to traditional processor-centric execution) using each of the strategies, highlighting differences in capabilities, target scenarios and implementation philosophies.

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12:00 - 12:30

Compute-in/near-Memory Systems with 2.5D/3D/3.5D Integration 

Chixiao Chen (Fudan University, CN)

The rapid expansion of large AI models, such as ChatGPT, has placed significant chanllenges on traditional computing architectures.  To overcome the memory wall memory-centric architectures such as Computing in/near Memory (CIM/PNM) have emerged, integrating computation and memory to reduce both latency and energy consumption. This talk explores the scalability of CIM/PNM systems through 2.5D/3D/3.5D heterogeneous integration enabled by advanced packaging techniques. In 2.5D integration, a layer-wise pipeline parallelism mapping is discussed, where inter-chiplet communication is minimized to improve efficiency. In 3D integration, the stacking interface promises enhanced bandwidth, reduced interconnect delays, and scalable performance for AI workloads. An active interposer-based 3D CIM system is developed to enable flexible 3D communication. The talk will also address the architectural and circuit-level challenges associated with designing active interposer-based systems. In 3.5D integration, an architecture-algorithm co-design approach is developed for decoder-only large language model (LLM) systems. The recent 3.5D PNM technology effectively addresses the extremely large memory access and tens of gigabytes of weight data required by these systems. These 2.5D/3D/3.5D approaches offer a viable path for sustaining advancements in scaling laws in the post-transistor-scaling era, with significant implications for AI infrastructure, edge computing, and high-performance systems.​​​

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12:30 - 13:00

A Fast and Energy-Efficient Near-Memory Computing Platform for FHE-Based Privacy-Preserving AI Applications 

Yoshihiro Ohba (KIOXIA, JP)

Securing data is vital as public and private organizations recognize it as an asset when collecting, using, and sharing information. For this reason, data protection regulations are growing worldwide, and the demand for global privacy and requirements is also increasing. Along with these trends, there is a highly increasing demand for secure computation, also known as privacy-preserving methods. Fully Homomorphic Encryption (FHE) is considered one of the most compelling technologies in secure computing. We present a FPGA-based fast and energy-efficient near-memory computing platform aiming for FHE-based privacy-preserving AI applications.​

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13:00 - 14:00

Lunch

 

Session 3: In-Memory Computing for Edge AI

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14:00 - 14:30

In-Memory Computing-Based Embedded Neural Processing Units for AI

Thomas Boesch (STMicroelectronics, CH)

Today’s SoC devices for consumer, industrial, and automotive applications often require integrated AI processing capabilities whereas Neural Processing Units (NPUs) based on classical digital architectures provide only limited compute density and energy efficiency of a few TOPs per Watt. With the advent of In-Memory Computing (IMC), those limitations can be lifted further and a boost in terms of energy and cost efficiency can be achieved. IMC functionality can be supported by on-chip SRAM tiles as well as Non-Volatile Memories (NVM) such as embedded Phase Change Memories (PCM) using digital or analog computing methods. While analog computing potentially provides better power efficiency it may generates implications for computation accuracy due to process, temperature, age, and voltage variations. Furthermore, techniques to improve storage density like multi-level memory cells can provide  opportunities to further improve the key metrics of TOPs/Watt or TOPS/mm². In general, the characteristics of the different IMC computing technologies are of great importance for the selection of the best edge AI device architecture and this workshop session will provide a deep dive into multiple aspects of using IMC in the context of AI edge computing.​

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14:30 - 15:00

Near/In-sensor Computation: from Processing to Generating 

Yongpan Liu (Tsinghua University, CN)

The rapid development of emerging applications, such as embodied intelligence, has driven unprecedented demand for data sensing. Compared with traditional architectures that separate sensing and computing, near/in sensor computing, demonstrates significant advantages in reducing energy consumption, minimizing data transfer, and enhancing sensor performance. Recent advancements in near/in sensor computing reveal a transformative shift from data processing to data generation. Prior researches have covered topics from processing architectures for single-modal data (e.g., visual or text signals) and those leveraging multi-modal sensor fusion for complementary cross-modal perception. However, these efforts remain constrained by the physical limitations of sensors, such as limited sensing dimensions or information loss caused by object occlusion. The latest breakthroughs overcome these constraints by integrating sensing with AI-driven data generation (e.g., via NeRF or 3D Gaussian Splatting). We have been focused on designing energy-efficient architectures for data processing and generating. This presentation will introduce our designed chips for multimodal fusion and generative perception. We will also show our avalanche-photodiode (APD) based pixel-level in-sensor computing system. Finally, we will discuss the implications of near/in sensor computation for future intelligent systems.​

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15:00 - 15:30

Brain‐Inspired On‐Device Learning and Event‐Based Processing at the Edge 

Charlotte Frenkel (TU Delft, NL)

Can key organizing principles of the brain be identified and exploited toward breakthroughs for intelligent devices at the edge? While the brain is still the gold standard in aspects ranging from adaptability to energy and data efficiency, exploiting brain insight is missing a clear framework. Should we start from the brain's computational primitives and figure out how to apply them to real-world problems (bottom-up approach), or should we build on working AI solutions and fine-tune them to increase their biological plausibility (top-down approach)? In this talk, we will (i) adopt a NeuroAI framework revealing how to reconcile both approaches, and (ii) show concrete outcomes, from event-based edge vision systems that can react within microseconds to tiny wearables that can autonomously learn how to classify gestures and keywords in real time within microwatts.​​

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15:30 - 16:00

Coffee break

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Session 4: Energy-Efficient Digital Accelerators

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16:00 - 16:30

Efficient Design Flows for Decoupled Dataflow Accelerators 

Marian Verhelst (KU Leuven, BE)

This talk presents efficient design flows for decoupled dataflow accelerators, enabling orthogonal optimization of data flow, scheduling, and memory layout in edge AI processors. By decoupling these components, each can be independently optimized to meet the demands of AI workloads.

We introduce automated generation of Multiply-Accumulate (MAC) arrays for high-performance computation and streamers for efficient data fetching from memory, reducing latency and maximizing bandwidth. Additionally, we explore automated data layout transformations that optimize memory organization for varying workloads. These hardware components are integrated with a customized compiler, enabling seamless translation of AI models into optimized hardware configurations. Our approach aims to achieve scalable, energy-efficient accelerators for edge AI applications. 

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16:30 - 17:00

Enhancing the Efficiency of Heterogeneous Edge‐AI systems: from HW/SW Accelerator Co‐Design to Workload Off‐Loading

Marina Zapater (HEIG‐VD University, CH)

Heterogeneous systems are a key enabler for moving Artificial Intelligence (AI) from the datacenter to the edge. Novel accelerators, such as in-cache and in-memory accelerators, and standard interconnects (such as PCIe, CXL and UCIe) are key for enhancing efficiency for both edge (energy-optimized) and HPC (performance-optimized) systems. A seamless path from software (SW) to hardware (HW) needs to be enabled to assess the overall SW-HW stack in terms of performance, power and thermal constraints. Architectural exploration using full-system simulations, such as gem5, turns out to be a key enabler to understand the power/performance trade-offs of Edge-AI systems and how to better exploit its capabilities. At the same time, the most resource-hungry workloads (such as LLMs) cannot be solely executed at the edge, and therefore required to be off-loaded either to edge servers or to data centers. In this talk I will be describe the challenges encountered to simulate full-stack state-of-the-art heterogeneous with novel accelerators and standard interconnects. I will highlight how a full-stack simulation framework enables to provide design guidelines and assess efficiency at all levels, enabling to exploit the benefits of hardware-software co-design, and describe machine-learning based techniques enabling workload off-loading from the edge to the cloud.​​

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17:00 - 17:30

Leveraging Domain-Specialized RISC-V Multi-core Processors for Heterogeneous AI Acceleration at the Edge

Angelo Garofalo (University of Bologna, IT)

Deploying modern AI workloads – including Transformers – to resource-constrained edge devices remains a significant challenge. To meet performance requirements within tight energy budgets, edge systems must rely on fast, low-bitwidth arithmetic. This talk explores how specializing RISC-V processors with domain-specific ISA extensions provides a low-cost solution for executing AI workloads on tiny edge devices. It also analyzes how specialized RISC-V multi-core architectures can complement the computing capabilities of analog and digital AI accelerators in tightly-coupled, scaled-up heterogeneous fabrics. As accelerators boost performance on linear kernels, specialized programmable cores play a key role in mitigating performance bottlenecks that arise per Amdahl’s effect in non-linear or fast-evolving functions – tasks less suitable to custom hardware acceleration. The talk addressed these challenges and provides design guidelines for next-generation edge AI platforms that balance flexibility, energy efficiency, and scalability.​

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