TUTORIALS
T5: Beyond 3nm: Pioneering CMOS Technologies from Individual Transistors to Full Circuits in the Angstrom Age
14:00 - 17:30
CHAIR
Hussam Amrouch (Technical University of Munich, DE)
ABSTRACT
The semiconductor industry is entering a transformative era as CMOS scaling advances beyond 2nm into the Angstrom regime. This tutorial explores key breakthroughs, including nanosheet and complementary FET (CFET) technologies, and the critical role of material-to-system co-optimization. We will address major reliability challenges such as aging and self-heating, highlighting how deep learning can revolutionize reliability estimation—from individual transistors to full-chip analysis—enabling massive acceleration. Additionally, we will demonstrate how deep neural networks (DNNs) can enhance compact modeling, significantly improving predictive accuracy and efficiency. Attendees will gain insights into the future of transistor scaling and AI-driven reliability modeling.
PROGRAM
13:00 - 14:00
Lunch
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14:00 - 15:30
Journey with Reliability Estimation from Individual Transistors to Full Chip
Hussam Amrouch (Technical University of Munich, DE)
As CMOS technology moves beyond FinFETs into advanced gate-all-around architectures like nanosheet and complementary FETs, reliability has become one of the biggest roadblocks to sustained performance and chip lifetime. This talk will explore the key degradation effects—self-heating, bias temperature instability (BTI), and hot-carrier injection (HCI)—that silently erode circuit robustness at advanced nodes. We will show how the induced degradations physical effects, while starting at the device level, can accumulate to impact the full processor implementation at the GDSII level—where timing and lifetime reliability must align. We will demonstrate how machine learning is becoming essential to accelerate reliability analysis across the entire design stack. ML enables fast, accurate prediction from transistor behavior to full-system performance, helping designers push performance limits without compromising reliability. This talk will connect the dots between device physics, circuit behavior, and system design—and offer a path to sustainable CMOS scaling in the age of AI.
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15:30 - 16:00
Coffee break
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16:00 - 17:30
Reliability Challenges in Sub-3nm Technologies: Material Implications and Device Impact
Luca Larcher (Applied Materials and University of Modena and Reggio Emilia, IT)​
Scaling technology below 3nm is facing unprecedented challenges at material, device and architecture level. Besides Power Performance Area Cost (PPACt) metrics optimization, also reliability is becoming increasingly important due to hard workload imposed by AI applications. This tutorial will focus on reliability issues of both Front-End-of-Line (FEOL) and Back-End-of-Line (BEOL). We will discuss the physical mechanisms governing device reliability from an atomic defect perspective, focusing on defect trapping and generation, and covering key reliability issues such as Bias Temperature Instability (BTI), Self-Heating Effects (SHE), Breakdown/Time-Dependent Dielectric Breakdown (BD/TDDB), and Electromigration (EM). Novel simulation-driven techniques will be presented to extract material properties such as process induced imperfections (e.g., atomic defects) from electrical data and physical metrology (e.g., XPS, FTIR). Such material/defect properties will be used for device performance and reliability prediction (including statistics), thus allowing linking material pathfinding/screening and process optimization to device reliability.
BIOSKETCHES
Hussam Amrouch
Hussam Amrouch is Professor heading the Chair of AI Processor Design within the Technical University of Munich. He is, additionally, the head of Brain-inspired Computing at the Munich Institute of Robotics. Further, he is the head of the Semiconductor Test and Reliability department at the University of Stuttgart, Germany. He is also the Academic Director of TUM Venture Labs.. He has over 300 publications (including around 130 articles in many top journals including Nature Communications) in multidisciplinary research areas covering semiconductor device physics, circuit design and computer architecture.
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Luca Larcher
Luca Larcher graduated in Electronic Engineering from the University of Padova, Italy, in 1998. He received his Ph.D. degree in “Information Engineering” from the University of Modena and Reggio Emilia in 2002. He was appointed as Assistance Professor in 2001, Associate Professor in 2005, and Full Professor of Electronics in 2017. In 2017, he co-founded a startup (MDLSoft Inc), which was acquired by Applied Materials in 2019. From April 1st 2019 he is with Applied Materials, as a Managing Director leading the Ginestra simulation S/W team. His current research interests include the modeling and characterization of electron devices with focus on physical mechanisms governing charge transport and material degradation. In the past, he worked also on RFIC and energy harvesting circuit design. He authored and co-authored one book and three book chapters, and more than 300 technical papers published on international journals and proceedings of international conferences (H factor 56). He has joined the technical and executive committees of the IEEE-IEDM (2006-2007, 2013-2015), IEEE-IRPS (2011-2012, 2017-2019) and IIRW (2013-2018, he served as General Chair in 2018).