TUTORIALS

Program to be structured according to the following schedule: 

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09:30 - 11:00

Session 1

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11:00 - 11:30

Coffee break

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11:30 - 13:00

Session 2

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13:00 - 14:00

Lunch

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14:00 - 15:30 

Session 3

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15:30 - 16:00 

Coffee break

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16:00 - 17:30 

Session 4

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Talks: ​

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DTC-Assisted Fractional-N PLLs 

Salvatore Levantino (Polytechnic University of Milan, IT)

Digitally-calibrated digital-to-time converters (DTCs), introduced in 2011, have fundamentally enhanced the jitter-power performance of fractional-N phase-locked loops (PLLs). Their ability to compensate for frequency-divider modulus modulation quantization error through digitally-controlled delay stages is key. The deterministic jitter caused by non-linear DTC characteristics has spurred the development of advanced solutions, including constant- and inverse-constant-slope DTC designs, DTC-range reduction methods, automatic digital pre-distortion, and dithering techniques.

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Fractional-N Phase-Locked Loops Using Harmonic-Mixer-Based Feedback and Noise Cancellation 

Tetsuya Iizuka (University of Tokio, JP)​

Frequency synthesizers are an integral part of various applications, such as wireless and wireline communication systems. The generation of frequency sources with low phase noise under limited power, area, and many other factors has been an ongoing challenge over the years. Especially for the fractional-N phase-locked loops (PLLs), the suppression of quantization noise (Q-noise) and spurs has been one of the main challenges. Architectures based on quantization error cancellation, either in the time domain using digital-to-time converters or in the voltage domain using digital-to-analog converters, have been popular in recent years. However, the circuits used for the cancellation are often affected by PVT-related gain errors and non-linearity, requiring intensive digital calibration to prevent severe performance degradation. In this talk, we introduce some harmonic-mixer-based fractional-N PLL architectures that avoid the amplification of the Q-noise by the loop. With this concept, we can effectively suppress the contribution of the Q-noise at the PLL output without applying intensive calibration. ​​

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Pushing the Performance Boundaries of All-Digital PLLs

Bogdan Staszewski (UCD, IE)

Over the past two decades, all-digital PLLs have proliferated across RF, millimeter-wave and high-performance frequency synthesis, driven by their advantages in flexibility, reconfigurability, transfer function precision, fast settling speed, frequency-modulation capability, and seamless integration with digital baseband and application processors. Nevertheless, the relentless pursuit of improved phase-noise performance in wireless and wireline industries has recently spurred research focused on reducing PLL loop latency, enhancing effective sampling rates, and improving overall transfer function linearity. In this talk, we present recent research achievements that push the PLL jitter into the deep 100-fs range while ensuring low reference and fractional spurs. The discussed techniques include charge-sharing locking, charge steering sampling, reference-waveform oversampling, and time-domain arithmetic-unit processing.​

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Low-Jitter Ring-Oscillator-Based Fractional-N Digital PLL

Jaehyouk Choi (Seoul National University, KR)

Modern SoCs for advanced wireless and wired transceivers are integrating an increasing number of PLLs onto a single silicon die. 5G transceivers require multiple PLLs to support complex carrier aggregation schemes and MIMO, while the number of wired interconnect lanes continues to rise to meet the data throughput demands of AI computing. In this context, area-efficient PLL design has become increasingly important. From the perspective of silicon efficiency, ring-oscillator (RO)-based digital PLLs (DPLLs) offer clear advantages over conventional LC VCO-based analog PLLs. RO-based DPLLs are also more scalable with advanced CMOS technologies and can be implemented in CMOS nodes that lack high-quality metal layers for inductors. However, despite these advantages, their limited jitter performance has constrained their use in high-performance applications that demand ultra-low-jitter clock signals. This talk explores strategies for designing low-jitter RO-based fractional-N DPLLs and introduces advanced techniques to address the associated challenges.​

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Linearization and low-jitter techniques in Digital-PLL based modulators

Luigi Grimaldi (Infineon Technologies , AT)

Digital PLLs are being more and more in the spotlight as suitable solution for phase/frequency modulators. The main reason resides in the versatility of the digital approach in implementing techniques capable of enhancing the overall system performance. The aim of this talk is to elaborate on the recent advances in this field mainly focusing on: linearization techniques based on digital pre-distortion schemes as the key to enable highly linear frequency synthesis (crucial in FMCW modulators), fast channel hopping and low spur operation; two-point modulation scheme to break modulation speed vs jitter trade-off; gain and phase mismatch correction techniques to preserve spectral purity; digital techniques for low jitter frequency generation. 

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Tools to better balance the tradeoffs in magnetic coupling with phase noise to enable compact low phase noise LCPLL designs

Mark Elzinga (AMD, US)​

In high data rate SERDES and many RF designs, there are two major competing requirements: a need for multiple LC PLLs or other clock generator circuits at close proximity which increases coupling jitter risk, while at the same time maintaining <50fs RJ RMS integrated phase noise for example.  The competing requirements are continuously driving a need for new architectures and new tools to mitigate coupling issues and maintain jitter performance, as well as enable scaling performance for future requirements.  The talk will cover multiple tools, architectures, and techniques to better balance the coupling/pulling mitigation with jitter performance.

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