PARALLEL SESSION
B3L-E
ML dataflow acceleration with SRAM compute-in-memory
WEDNESDAY - 10 September | 10:25 - 12:05
CHAIRS
Hongyang Jia, Joachim Rodrigues
SESSION PROGRAM
10:25 - 10:50
EPIC: A Sub-6mW In-Memory Computing-Based RISC-V Microcontroller Unit with On-Chip Training Support for TinyML
Chuan-Tung Lin, Seunghyun Moon, Paul Xuanyuanliang Huang, Mingoo Seok
10:50 - 11:15
SRAM Compute-in-Memory Macro with Dual-Dataflow Architecture for Efficient Support of Multi-Modal Transformers and CNNs
Tianqi Wang, Zhongheng Xie, Massimo Alioto
11:15 - 11:40
An LLM-Friendly CIM-Based Transformer Accelerator with Multi-Head Adaptable Computation Scheme
Yi-Hsuan Pan, Hsin-Yu Liu, Ping-Hsuan Huang, Wei-Cheng Chen, Yue-Long Yu, Jyun-Jhe Chou, Xin-You Liu, Chieh-Fang Teng...
11:40 - 12:05
A 56.2TOPS/W Hybrid-Inner-Outer-Product SRAM Compute-in-Memory Macro for GEMM with Scalable Precision-Adaptive Systolic Dataflow
Wenjie Ren, Meng Wu, Xiangjun Ye, Ruohang Xu, Peiyu Chen, Ying Liu, Fengyun Yan, Jiayoon Ru, Yufei Ma, Tianyu Jia, Le...