TUTORIALS

Kavya Sreedhar (Chair)

Kavya Sreedhar is a Research Scientist in the Machine Learning Performance team at Google. At Stanford, she received her PhD in electrical engineering, advised by Mark Horowitz, in 2025, and her MS in electrical engineering in 2020. She received a BS in electrical engineering and a BS in business, economics, and management from Caltech in 2019. Her graduate school research was supported by Stanford's Knight-Hennessy Graduate Fellowship and the Quad Fellowship. She previously interned with Meta Reality Labs, NVIDIA's Architecture Research Group, Apple, Microsoft, and Intel. Her research interests are broadly in hardware design for machine learning and cryptography applications. 

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Thierry Tambe (Chair)

Thierry Tambe is an Assistant Professor of Electrical Engineering and, by courtesy, of Computer Science at Stanford University. His research explores the intersection of AI/ML and hardware systems. Specifically, his research group develops algorithms, hardware architectures, chips, and tools to make accelerated AI computing more portable, scalable, efficient, and easier to design. Previously, Thierry was a visiting research scientist at NVIDIA and an engineer at Intel. He received a B.S., and M.Eng. from Texas A&M University, and a Ph.D. from Harvard University, all in Electrical Engineering. 

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Amir Zjajo (Chair)

Amir Zjajo is co-founder of Innatera Nanosystems B.V., and serves as its Chief Scientist. Prior to that, he was a member of research staff in the Mixed Signal Circuits and Systems Group at Philips Research Laboratories between 2000 and 2006, and subsequently, with Corporate Research at NXP Semiconductors until 2009. He joined the Delft University of Technology the same year as a Senior Lecturer, and was responsible for leading research into intelligent circuits and systems. Dr. Zjajo has published 3 books, more than 90 papers in referenced journals and conference proceedings in the areas of mixed-signal VLSI design, and neuromorphic circuits and systems, and holds more than 20 US patents or patent pending. He served as a TPC member of ISQED, DATE, VLSI Symposium, ISCAS, and BioCAS, among others. He received the M.Sc. and DIC degrees from the Imperial College London, London, U.K., in 2000, and the PhD. degree from Eindhoven University of Technology, Eindhoven, The Netherlands in 2010, all in electrical engineering. His research interests include energy-efficient circuit and system design for neuromorphic signal processing, and bionic electronic circuits for autonomous cognitive systems. 

Dr. Zjajo won best/excellence paper award at BioDevices’15, LifeTech’19 and AICAS’23. He is a senior member of IEEE. 

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Francesco Conti

Francesco Conti holds the position of Associate Professor of Electronics in the Department of Electrical, Electronic, and Information Engineering at the University of Bologna, Italy. He completed his Ph.D. in electronic engineering at the same university in 2016 and worked as a Post-Doctoral Researcher at ETH Zürich between 2016 and 2020. His research is centered on hardware acceleration in ultra-low power and highly energy efficient platforms, with a particular focus on System-on-Chips for Artificial Intelligence applications. He is a senior contributor to the open-source PULP Platform project initiative, and has focused also on technology transfer, most notably as a consultant for the development of the GAP9 System-on-Chip with GreenWaves Technologies. Over his career, he has contributed to over 100 international conference presentations and journal articles, earning him multiple accolades, such as the 2020 IEEE Transactions on Circuits and Systems Darlington Best Paper Award and the 2018 ESWEEK CODES+ISSS Best Paper Award. He is a Senior Member of IEEE and a member of the IEEE Circuits and Systems Society, Solid-State Circuits Society, and Council for Electronic Design Automation. He serves as Associate Editor for the IEEE Transactions on Computer-Aided Design of Circuits and Systems and as committee member in ISSCC (2025-ongoing), ESSERC (2023-ongoing), and DATE (2022-ongoing, E3 topic chair since 2024). 

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Aditya Dalakoti

Aditya Dalakoti received B.Tech in Electrical Engineering from Indian Institute of Technology, Ropar in 2014, and MSc and PhD in Mixed-Signal VLSI from University of California Santa Barbara in 2016 and 2018, respectively. He has co-authored 10 papers in various IEEE conferences and Journals. 

He was previously with the LiDAR design division of Continental in Carpinteria, California, where he was involved in the ReadOut ASIC design projects from 2018 to 2020. He later moved to the Netherlands to join Innatera in 2020. As Principal Engineering Manager, Dr. Dalakoti has led ground-breaking technical developments across Innatera's analog-mixed signal computing technology portfolio. 

Aditya Dalakoti received B.Tech in Electrical Engineering from Indian Institute of Technology, Ropar in 2014, and MSc and PhD in Mixed-Signal VLSI from University of California Santa Barbara in 2016 and 2018, respectively. He has co-authored 10 papers in various IEEE conferences and Journals. 

He was previously with the LiDAR design division of Continental in Carpinteria, California, where he was involved in the ReadOut ASIC design projects from 2018 to 2020. He later moved to the Netherlands to join Innatera in 2020. As Principal Engineering Manager, Dr. Dalakoti has led ground-breaking technical developments across Innatera's analog-mixed signal computing technology portfolio. 

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Wim Dehaene

Wim Dehaene obtained his PhD from KU Leuven, Belgium, in 1996 respectively. Presently, he is a full professor and head of the MICAS division of KU Leuven. His research domain is circuit level design of digital circuits. The current focus is on ultra low power signal processing and memories in advanced CMOS technologies. Part of Wim Dehaene’s research is performed

in cooperation with IMEC, Belgium, where he is also a part time principal scientist. He is also leading the circuit design aspects in several biomedical IC design projects. Wim Dehaene is a senior member of the IEEE. He is a member of the ESSERC steering committee. He was the general chair of ESSERC 2024. He has also served for several years on the ISSCC program committee. 

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Charlotte Frenkel

Charlotte Frenkel is an Assistant Professor at Delft University of Technology, The Netherlands, since July 2022, and a Visiting Faculty Researcher at Google since October 2024. She received her Ph.D. from Université catholique de Louvain in 2020 and was a post-doctoral researcher at the Institute of Neuroinformatics, UZH and ETH Zurich, Switzerland. Her research aims at bridging bio-inspired and engineering-driven design approaches toward neuro-inspired AI systems, with a focus on digital neuromorphic processor design, embedded machine learning, and on-device learning. Dr. Frenkel serves or has served in the technical program committee of various conferences such as DATE, ESSERC, and NICE, co-leads the NeuroBench initiative for benchmarks in neuromorphic computing, and is an associate editor for the IEEE Transactions on Biomedical Circuits and Systems.

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Anna Goldie

Anna Goldie is a Senior Staff Research Scientist at Google DeepMind. She currently works on Gemini, and her research interests lie at the intersection of LLMs and RL. Previously, she worked on LLM research at Anthropic and co-founded/led the ML for Systems team in Google Brain, where she developed deep reinforcement learning approaches to problems in computer systems and chip design. At MIT, she earned a Bachelors of Computer Science, a Bachelors of Linguistics, and a Master of Computer Science, and she is a CS PhD Candidate in the Stanford NLP Group. She was named one of MIT Technology Review's 35 Innovators Under 35. Her work has been published in Nature, NeurIPS, ICLR, EMNLP, ISPD, ASPLOS, SysML, and MLCAD, and has been covered by CNBC, ABC News, IBTimes, WIRED, MIT Technology Review and IEEE Spectrum. 

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Sangyeob Kim

Sangyeob Kim received his B.S., M.S., and Ph.D. degrees from the School of Electrical Engineering at the Korea Advanced Institute of Science and Technology (KAIST) in Daejeon, South Korea, in 2018, 2020, and 2023, respectively. From 2023 to 2025, he was a Post-Doctoral Research Associate with the Information and Electronics Research Institute, KAIST. Now, he is currently an Assistant Professor with the School of Integrated Technology, Yonsei University, Seoul, South Korea. His current research interests include energy-efficient AI semiconductor chip design, especially focused on accelerators for deep neural network, neuromorphic computing, and large language model. Dr. Kim has served as a member of the Technical Program Committee for the Design Automation Conference (DAC) and the Review Committee for the International Symposium on Circuits and Systems (ISCAS). 

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Johannes Leugering

Johannes Leugering is a postdoc researcher in Prof. Gert Cauwenbergh’s Integrated Systems Neuroengineering Lab at UC San Diego, working on mixed-signal neuromorphic computing systems and event-driven algorithms. He received his PhD in computational neuroscience from University Osnabrück on models of neural and dendritic computing, and he spent four years in applied research as Chief Scientist of the Broadband and Broadcast Department and deputy group leader of the Embedded AI group at the Fraunhofer Institute for Integrated Circuits in Erlangen, where he developed mixed-signal accelerators and algorithms for (spiking) neural networks.

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Shih-Chii Liu

Shih-Chii Liu received the BS degree in electrical engineering from MIT and the PhD degree in the Computation and Neural Systems program from Caltech. She is Adjunct Professor in the Faculty of Science at the University of Zurich, Switzerland. She co-directs the Sensors group (https://sensors.ini.ch) at the Institute of Neuroinformatics, University of Zurich and ETH Zurich. Her group works on ASIC design of low-power neuromorphic auditory sensors, event-driven bio-inspired processing models and deep neural network algorithms; and the use of these networks in neuromorphic artificial intelligent systems. Dr. Liu is past Chair of the IEEE CAS Sensory Systems and Neural Systems and Applications Technical Committees. She is past associate editor of the IEEE Transactions of Biomedical Circuits and Systems and Neural Networks journal. She was the general co-chair of the 2020 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) and a technical committee member of 2023 IEEE AICAS. She has been current Chair of the IEEE Swiss CAS/ED Society and is a technical committee member of 2025 IEEE Custom Integrated Circuits Conference (CICC). 

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Christian Mayr

Christian Mayr received the Dipl.-Ing. (M.Sc.) in Electrical Engineering in 2003, his PhD in 2008 and Habilitation in 2012, all three from Technische Universitätt Dresden, Germany. From 2003 to 2013, he has been with Technische Universität Dresden, with a secondment to Infineon (2004-2006). From 2013 to 2015, he was a group leader at the Institute of Neuroinformatics, University of Zurich and ETH Zurich, Switzerland. Since 2015, he is full professor at TU Dresden, head of the Chair of Highly-Parallel VLSI Systems and Neuromorphic Circuits. His research interests include computational neuroscience, bio-inspired artificial intelligence, brain-machine interfaces, AD converters and general System-on-Chip design. He is author/co-author of over 180 publications and holds 4 patents. He is a PI in two German excellency clusters, in the federal German AI compute center Scads.AI and in the EU flagship Human Brain Project. He has co-founded

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Azalia Mirhoseini

Azalia Mirhoseini is an Assistant Professor of Computer Science and founder of Scaling Intelligence Lab at Stanford University. Her lab develops scalable and self-improving AI systems and methodologies towards the goal of advancing artificial general intelligence. She also spends time at Google DeepMind as a Senior Staff Scientist. Prior to Stanford, she spent several years in industry AI labs, including Anthropic and Google Brain. Her past work includes Mixture-of-Experts (MoE) neural architectures, now commonly used in frontier generative AI models, and AlphaChip, a pioneering work in agentic AI for chip design which has been used in the design of advanced AI accelerators such as TPUs and data center CPUs. Her work has been recognized through the MIT Technology Review’s 35 Under 35 Award, the Best ECE Thesis Award at Rice University, publications in flagship venues such as Nature, and coverage by various media outlets, including MIT Technology Review, IEEE Spectrum, The Verge, The Times, ZDNet, VentureBeat, and WIRED. 

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Johannes Schemmel

Johannes Schemmel has been head of the “Electronic Visions” research group at the Kirchhoff-Institute für Physik since 2000 and of the ASIC-Laboratory at Heidelberg University since 2008. Currently he holds the chair in “Neuromorphic Computing Architectures” at the institute of computer engineering at Heidelberg University (ziti). His research focus is on highly parallel mixed-signal circuits for information processing, specifically the analog implementation of biologically inspired neural networks. His research group pioneered wafer-scale implementation of analog neuromorphic processors. It operates the Heidelberg neuromorphic BrainScaleS system as part of the EBRAINS research infrastructure.

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George Vathakkattil Joseph

George Vathakkattil Joseph is currently Product Architect at Innatera Nanosystems, where he is responsible for defining and validating new product components, across hardware and software stacks, along with reference application development. He has worked extensively with audio and IMU signals, efficient training methods for tinyML, and deployment on heterogeneous SoC architectures. 

Prior to joining Innatera, George completed his Ph.D. in 2020 at University College Dublin focusing on non-von-Neumann computing architectures using coupled oscillator networks. His research interests span synchronization in complex systems and networks, combinatorial optimization, and spiking neural networks. He has held various research positions at Indian Institute of Science Bangalore, Indian Institute of Technology Madras and National Chiayi University Taiwan since 2015. He completed his B.Tech degree in Engineering Physics from National Institute of Technology Calicut in 2015. He has co-authored multiple peer reviewed journal articles, has been a speaker/presenter at various academic and industry conferences. 

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​Sai Qian Zhang

Sai Qian Zhang is an Assistant Professor of Electrical Engineering and Computer Science at New York University. Prior to joining NYU, he spent two years at Reality Labs at Meta. Sai earned his Ph.D. from Harvard University in 2021 and holds both M.A.Sc and B.A.Sc degrees from the University of Toronto. His research interests include efficient machine learning algorithms and systems and AR/VR computing. 

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